Hello and Welcome,
I am very pleased to introduce you to the first issue of Advantest’s new newsletter, ATenews and would like to welcome you as a subscriber. Published quarterly, ATenews will keep you up-to-date on new test solutions and industry and Advantest events around the world as well as give you insights on test trends. The increased pace of our industry’s progress makes it critical for us to have timely, relevant information in order to make the best technological and business decisions. We promise to keep the quarterly issues short and to the point, and invite your feedback: newsletter@advantest.com. Hope you enjoy the first issue and hope to hear from you.

R. Keith Lee
President and CEO, Advantest America

TOPPress Corner

Advantest Receives Intel's Preferred Quality Supplier Award
Read more »

Advantest’s 16-Channel Mixed-Signal Module for SoC Test Wins Best in Test Honorable Mention
Read more »

Advantest Introduces Low-Cost SoC Test Solution for T2000 Open Architecture Platform
Read more »

Advantest Launches M4841 Dynamic Test Handler
Read more »

Advantest Announces Plans to Relocate Production Facilities
Read more »

Cadence, Advantest Address Zero-Defect Test Requirements for Automotive Electronics
Read more »

TOPProduct Highlights

T2000 LS: New Low-Cost Consumer Device SoC Test Solution for T2000 Open-Architecture Test Platform Read more »

M4841: High-Throughput Device Handler for Volume Production Testing of MCUs and DSPs Read more »

TOPRecent Papers and Articles:

Needed: New Thinking for Wireless/RF Testing, by Keith Schaub
Test & Measurement World Magazine, April 2007
SOC (System On a Chip) and SIP (System In a Package) have presented test challenges with most existing testers addressing either the SOC market with high-end, high-cost configurations –or SIPs with focused, low-end configurations. Increasingly the worlds of SOC and SIP are converging, creating a new challenge requiring new testing practices and the need for testers that can be quickly and easily reconfigured to address either or both.
Read more »

Get Higher ATE Throughput at Lower Costs, by Doug Lefever
Test & Measurement World Magazine, March 2007
The most promising area for significant improvements in cost of test is in the handler. The latest generation of handlers has improved the speed with which devices can be moved from tray to socket and socket back to tray while avoiding jams and device damage. A recently introduced handler doubles the capacity of earlier handlers, with parallel test of up to 16 devices and high throughput of 18,500 devices per hour at 3 seconds or less.
Read more »

A Model for Determining ATE Cost of Ownership, by Doug Lefever
Future Fab Issue 22, January 2007
In semiconductor automatic test equipment (ATE) decision making and selection, once equipment is proven to be technically capable of providing the necessary test coverage, the critical deciding factor becomes the equipment’s cost of ownership (CoO). Now more than ever, technical differentiators are revealed in the form of cost advantages, rather than ability vs. inability to test the part.
Read more »

Managing Post-Production Test Data, by Paul Roddy and Andre Leininger
Future Fab Issue 22, January 2007
Data collection during production test and data post-processing is getting the growing attention of the semiconductor industry. Two main trends are responsible for this: Analyzing production test data off-line by statistical methods -- e.g., to identify reliability risks and to reduce or replace burn-in -- and generating data for yield learning purposes.
Read more »

Evolutionary Changes for RF Device Testing, by Keith Schaub and Anthony Lum
Evaluation Engineering, November 2006
With the demand for more functionality at less cost, the RF testing landscape is evolving into a new frontier. In the cellular space, the convergence of services continues at an accelerated rate with consumer service providers and product manufacturers releasing new products that crossover between the PC and handset markets. Wireless/RF price erosion has burdened ATE companies to develop newer and better test strategies.
Read more »

System Integration of an Open-Architecture Test System By Yuhai Ma
Semiconductor Manufacturing, July 2006
Truly open architecture ATE – that is, test system architecture having specifications open to the public for unrestricted third-party module development – raises various challenges to the test industry, among them configuration, initialization, and synchronization; calibration and diagnostics; pattern compilation and loading; and system integration.  System integration is critical to ensure the performance and reliability of an entire, complex ATE system, with open architecture ATE adding even more challenges since it provides third-party vendors the opportunity for developing test instrument modules. The system integrator must combine these test modules to build a system while also guaranteeing its performance.
Read more »

Consumer Electronics Transform Chip Test Industry, by R. Keith Lee
Future Fab Issue 21, July 2006
Innovative, sophisticated consumer electronics products are the new major market for ICs and have changed the dynamics of the entire semiconductor industry, including test equipment. The dominance of consumer electronics in the IC business has accelerated the normal business model factors -- cyclical demand, pricing pressures and technology improvements – and presents a number of challenges to traditional test.  
Read more »

Addressing the Flash Memory Challenge, by Gary Fleeman
Evaluation Engineering, March 2006
The rapid growth of consumer products is fueling rapid growth for NAND flash memory, surpassing NOR revenues for the first time. Intense price competition in the consumer market means tight margins for the semiconductor industry, especially subcontractors, making high utilization of capital equipment such as ATE critical. The industry faces the triple challenge of a fast-moving market, new flash and technology test requirements and lowered cost of test for the consumer segment.
Read more »

New Trends Drive ATE Open Architecture, by Y. Furukawa
Semiconductor International, July 2005
In the nanometer era, new semiconductor manufacturing processes, such as copper interconnects, high-k gate dielectrics and low-k passivation, have become necessary. These processes, in tandem with optical proximity correction in nanoscale geometries, are creating an increasing number of new failure modes. New failure modes, however, cause variations in delay, crosstalk among signals, spurious transients, and many other faults that are sometimes hard to define. Such failure modes require engineering judgment criteria to reflect the variables in the manufacturing process, as well as an awareness of how the device operates.
Read more »

Happenings
TOPRecent and Upcoming Events

Global STC Meeting
Date:  May 14-16, 2007
Place:  Marriott Napa Valley, Napa, CA
Read more »

IEEE European Test Symposium (ETS)
Date: May 21-23, 2007
Place: Freiburg, Germany
Read more »

Semicon West 2007
Date:  July 16-20, 2007
Place:  Moscone Center, San Francisco, CA
Booth Number:  7347
Read more »

International Test Conference
Date:  October 23-25, 2007
Place:  Santa Clara Convention Center, Santa Clara, CA
Read more »

Investor Information
Read more »

TOPTraining

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