New products to offer greater ATE platform efficiencies, providing reduced test costs, and improved time-to-market and time-to-yield
TOKYO, JAPAN - November 30, 2010 - Advantest Corporation (TSE: 6857, NYSE: ATE) announced it will take advantage of the opportunity provided by Semicon Japan to preview three new modules and an infrastructure enhancement, named Enhanced Performance (EP) Package, for the T2000 SoC test platform.
The EP Package and the new module designs support Functional Test Abstraction (FTA), enabling test engineers to execute system level IC design verification programs on ATE, substantially reducing the lead time from design to functional testing of complex SoCs at the protocol level. In addition, the new 1GDM module, DPS90A module, and GPWGD module offer twice the parallel test capability of previously available modules by featuring 2x greater resources per module, and allowing a maximum of 8192 pins to be installed in the test head. The new EP Package will enable multi-site CPU configurations with near zero compute overhead for the same cost as the previously available single-site CPU configurations, improving throughput, reducing test costs, and time-to-market (TTM), while facilitating easy test program development, simulation, and debugging. Customers are invited to preview these new technologies at SEMICON Japan 2010, December 1-3, at Chiba’s Makuhari Messe.
While sales of PCs, cellular phones, and other electronics are soaring across the developing world, semiconductor ASPs are in decline. The increasing integration of multi-functional ICs for mobile devices, combined with the accelerating trend for chip-makers to enhance competitiveness by adding functionality, is driving the need for test solutions which can lower test costs and help shorten TTM. Advantest’s new modules and EP Package respond to these needs by further enhancing the performance of the T2000, Advantest’s flagship SoC test platform. By installing the three new modules, users can reduce the number of instruments used, while doubling the parallelism of previous solutions. The new EP Package helps to reduce test costs and time-to-yield with expanded functionality that enables existing T2000 users to implement true concurrent test, reduced compute overhead and increase system utilization for test debug and production test.
Advantest's new 1GDM module incorporates 256 channels, twice the number offered by the previously available 800MDM (digital module), with data rates increased to a maximum 1.1Gbps.
The DPS90A module is a single-module configuration, in contrast to the previously available LCDPS/DPS500mA module (a two-module configuration). This highly integrated design allows the DPS90A module to support a total of 64 DPS channels.
The GPWGD module consolidates the previously available AAWGD and BBWGD modules into a single highly integrated configuration, enabling full-spec test of high-performance audio and video functions.
- Low-Cost Multi-Site CPU Configuration
The multi-site CPU configuration allows users to efficiently and rapidly carry out adaptive test and other methodologies calling for different tests to be performed on each DUT. It enables efficient parallel test, reducing the overhead associated with massive parallelism.
- Concurrent Test Function
The EP Package includes a computing architecture that enables simultaneous execution of multiple test flows, allowing users to dramatically reduce test time by implementing concurrent test methodology.
- Functional Test Abstraction
The 1GDM module and the EP Package enable execution of system level design verification programs on ATE reducing the lead time between design to functional testing of complex SoCs at the protocol level.
- 1GDM (1Gbps Digital Module)
Channels : 256 per module
Max. Datarate : 1.1Gbps
Pattern memory : 128MW / 256MW
- DPS90A (Device Power Supply 90A)
Power source : 2A x 32 channels, 0.8A x 32channels
Supports high-accuracy ISVM
- GPWGD (General Purpose Waveform Generator and Digitizer)
Waveform Generators : 8 (1Msps/50Msps)
Digitizers : 8 (1Msps/50Msps)
Supports DC linearity test
- EP Package
Multi-site CPU : max. 8 sites
Module support : max. 52
Bus speed : 4Gbps
Supports concurrent test and functional test abstraction
Note: All information supplied in this release is correct at the time of publication, but may be subject to change without warning.