Company’s Universal Pin Architecture Enables Massively Parallel Testing in a Single System
TOKYO, Japan – Nov. 7, 2012 – Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857, NYSE: ATE) has introduced its new T2000 Integrated Massive Parallel test solution (IMS), a massive parallel test system capable of achieving the lowest cost of test for microcontroller units with integrated analog and embedded flash memory circuits. The new tester will be featured in Advantest’s exhibit (booth #8C-901 in Hall 8) at the SEMICON Japan trade show, December 5-7 in Makuhari Messe in the Chiba prefecture.
Designed to enable large-scale testing of up to 256 devices simultaneously, Advantest’s new integrated massive parallel test solution achieves high throughput and fast test times with a parallel efficiency target of more than 99 percent. The tester’s universal pin architecture internally manages 208 channels of diverse resources to provide optimal flexibility.
“With our new T2000 IMS system’s highly efficient and massive parallel production capabilities, we are positioned to capture even more market share in the cost-sensitive MCU (microcontroller unit) and Smart Card IC space,” said Dr. Toshiyuki Okayasu, executive officer and executive vice president of the SoC Test Business Group at Advantest Corporation. “The advantage lies in Advantest’s universal pin architecture. Other ATE companies need several modules and highly complex performance boards to manage those multiple modules in order to do the same job as our monolithic IMS module.”
Advantest’s design not only lowers the cost of test by simplifying the design of performance boards, but also reduces recurring manufacturing costs at production facilities because the universal pin architecture makes performance boards easier to maintain - a key performance attribute for overseas production facilities.
Note: All information supplied in this release is correct at the time of publication, but may be subject to change without warning.