Test Industry Market Leader to Exhibit Newest IC and AI Test Solutions and Feature Prominently in ITC's Renowned Technical Program
SAN JOSE, Calif. – November 4, 2019 – Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) will demonstrate its hardware, software and online test solutions and participate with paper, panel and poster contributions at the 2019 International Test Conference (ITC), taking place November 12-14 at the Marriott Washington Wardman Park Hotel in Washington, D.C.
Advantest is once again a platinum-level corporate supporter of ITC as well as a sponsor of the 50th Celebration on the evening of November 12 and the Test Technology Technical Council's (TTTC) Automotive Reliability and Test (ART) Workshop on November 14-15.
Advantest's booth #209 will feature demonstrations of its on-demand CloudTesting™ Service, the latest capabilities of its EVA100 low-cost analog/digital IC test solution, a new EVA stimulus tester for automotive current sensors, and a new tool that combines cloud and real-time edge-computing artificial intelligence (AI).
The innovative, first-of-its-kind CloudTesting™ Service allows users to access various test-method IP selections on Advantest's website whenever needed. Using this on-demand online service, designers can verify their new silicon at a very low cost with no capital investment, set up their own test environments within a few hours and be ready to test when the device arrives from the fab. With free tester leasing and minimum maintenance costs, Advantest's CloudTesting™ Service allows customers to avoid unplanned expenses.
Advantest's EVA100 analog/mixed-signal test solution combines a modular architecture with high-voltage and high-precision analog parametric measurement units, providing the flexibility to conduct various measurements over a broad range of analog and mixed-signal devices. The versatile, small-footprint EVA100 tester is easy to use for device characterization through volume production. The scalable architecture can be quickly reconfigured to address a varied product portfolio and achieve lower cost benefits from economies of scale.
In addition to product exhibits, Advantest experts will discuss the latest test technologies over the course of ITC's technical program with the following presentations and posters:
Posters Wednesday, November 13, 11:30 a.m. to 1:30 p.m. in Exhibit Hall
- PO 5: CloudTesting™ Service Enables Board-Level Post-Silicon Debug
- R. Radhakrishnan, A. Kashyap, S. Panigatti, Y. Oyama, A. Sivaram
- PO 7: High-Volume Consumer Devices Need High-Voltage Test Solution
- A. Lum, B. Wang, R. Waikar, A. Sivaram
- PO 46: An Effective INL Test Methodology for Low-Sampling-Rate and High-Resolution Analog-to-Digital Converter
- K. Sato, T. Ishida, T. Okamoto, T. Ichikawa, H. Kobayashi, K. Hatayama, T. Nakatani, A. Kuwana, J-L. Wei, N. Kushita, H. Arai, L. Sha
Technical Program Monday, November 11, 2:00 p.m. in Washington 4
- Test Challenges Meeting
- Hosted by Jeff Rearick, AMD
Wednesday, November 13, 3:00 p.m. to 4:30 p.m. in Washington 2
- Shifting Left for True KGD
- D. Armstrong
Wednesday, November 13, 3:00 p.m. to 4:30 p.m. in Washington 4
- Paper 8.3: A Jitter Injection Module for Production Test of 52-Gbps PAM-4 Signal Interfaces
- K. Ichiyama, T. Kusaka, M. Ishida
Thursday, November 14, 1:30 p.m. to 3:00 p.m. in Washington 2
- Paper 10.3: A New Test Method for Large-Current Magnetic Sensors
- T. Omuro, S. Nakamura, T. Kimura, T. Kiyokawa
Thursday, November 14, 3:00 p.m. to 4:30 p.m. in Ballroom
- Panel: Roadblocks for the Hetrogeneous Integration Roadmap in Test
- D. Armstrong, Panelist
- Invited Visionary Talk: Semiconductor Test – Towards a Data Driven Future
- K. Schaub
The latest information from Advantest is available on Twitter @Advantest_ATE.