T5230 memory test system for NAND/NVM devices adopts a combined array architecture to achieve best-in-class cost-of-test performance for wafer test, including wafer-level burn-in
(WLBI) and built-in self-test (BIST). The system can perform on-wafer test of 1,024 memory devices per test head in parallel, delivering high productivity and enabling floor space
savings of up to 86%. Multiple test cells are connected per system controller in the T5230, allowing independent wafer test of each test cell. The test cells can be stored in a general
multi-wafer prober while minimizing the test cell floor space, and the tester can be docked with probers in both linear and multi-stack configurations. For functional tests at a
maximum test rate of 125MHz/250Mbps, the T5230 assures high timing accuracy, repeatability, and failure detection capability.
As the capacity of 3D NAND devices increases, increased amounts of data output as test results have become harder to contend with. To offset the effects of these increases in data
processing time, the T5230 delivers higher data transfer speeds. As a result, test times can be further shortened and throughput is improved over previous products.
The T5230 uses Future Suite, an operating system for memory test systems that has a proven track record as the global standard. High compatibility with older systems provides users
with a seamless transition from previous generations of equipment.
