Digital Channel Card Enables Fast, Cost-Efficient Testing of ICs
in Both Engineering and Manufacturing Environment
TOKYO, Japan - March 19, 2014 - Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857, NYSE: ATE) has received an order from the engineering group within HiSilicon Technologies Co., Ltd., a Chinese producer of application-specific integrated circuits (ASICs) and other chipsets for communication networks and digital media, for a V93000 Smart ScaleTM tester equipped with Advantest's Pin Scale Serial Link (PSSL) digital channel card. Introduced in the fourth quarter of 2013, the PSSL card is already in use at more than 10 customer sites for both device characterization and volume manufacturing of today's most advanced high-speed semiconductors.
"Advantest's test solution presents both the performance capabilities and the low cost of test that we require," said David Lin, senior test manager with HiSilicon. "While we are installing a PSSL-enabled tester in our engineering operations, our OSAT (outsourced semiconductor assembly and test) partners are using several of these systems for high-volume testing of our commercially available ICs."
Operating at data-transfer rates up to 16 Gbps, PSSL is the fastest fully integrated automatic test equipment (ATE) instrument on the market. It is the newest of Advantest's Pin Scale cards built on the V93000 Smart Scale's universal pin architecture, making it capable of performing per-pin testing with high multi-site efficiency. Each pin on a PSSL card can run at its own data rate, allowing a tester to match the exact clock speeds of any device under test without sacrificing pin count or timing flexibility. This design enables the system to achieve unprecedented granularity in IC testing.
Because all resources can operate independently and simultaneously, PSSL is capable of high-volume throughput. The system can conduct affordable, at-speed testing of high-end ICs used in infrastructure and network processing applications including 10G/40G/100G Ethernet, PCI Express (PCIe) interface and proprietary 10G to 16G backplane SerDes technology, which is used in China's LTE communications infrastructure.
PSSL also supports a full suite of physical layer (PHY) testing methodologies such as pseudorandom bit stream (PRBS) stimulus and response, jitter injection and measurement capability as well as AC and DC analysis to provide comprehensive margin test coverage.
Note: All information supplied in this release is correct at the time of publication, but may be subject to change.