Memory Test System
T5833 system is a cost-efficient, high-volume test solution capable of performing both wafer sort and final test of DRAM and NAND flash memory devices.
Amid surging sales of mobile electronics, DRAMs, NAND flash memories and multi-chip packages (MCPs) — the main device types used in smart phones and tablets — are quickly evolving toward higher speeds and greater device capacity. Internet and cloud servers also are driving demand for faster, higher-capacity ICs. Yet the cost of testing today's wide array of memory devices is an obstacle for chipmakers, which urgently require solutions that can deliver high functionality, high performance and low cost of test (COT). Advantest's new, multifunctional T5833 memory test system meets these needs, delivering both wafer sort and final test capabilities for a full range of memory devices, including LPDDR3-DRAMs, high-speed NAND flash memories and next-generation non-volatile memory ICs.
With a parallel test capacity of 2,048 devices for wafer test and 512 devices for final package test, the T5833 lowers costs by significantly reducing test time and boosting throughput. In addition to supporting known good die (KGD) testing at a maximum speed of 2.4 gigabits per second (Gbps), the T5833 also features a flexible site CPU architecture with multiple CPUs that enables optimized control of test processes.
The new system offers industry-leading capabilities in high-speed failure address storage and failure analysis, also known as memory redundancy. The speed of these two functions, both of which are indispensable for wafer sorting, reduces test time while enabling the recovery of more ICs for improved yield. In addition, both operations are scalable by making adjustments such as adding more CPUs for calculations.
Utilizing Advantest's AS modular memory test platform, the T5833 allows customers to choose the optimal system configuration for their needs, from engineering stations to large, volume-production systems. This extendibility allows the T5833 to handle future generations of devices and achieve higher throughput, which provides greater return on investment.
|Target Devices||DRAM, NAND Flash|
|Parallel Testing||Wafer sort: 1,024 (x5IO)
Final test: 512 (x8IO)
|Test Speed||Up to 2.4Gbps|
|Overall Timing Accuracy||±75ps|
|Software||FutureSuite OS (ATL and MPAT compatible)|