Memory Test System
New test system optimized for use with a multi-wafer prober, for non-volatile memory ICs
The T5521 is a memory test system that supports wafer test and wafer burn-in test of non-volatile memory devices such as NAND flash, housed within a multi-wafer prober to reduce test floor footprint.
Dramatically reduces test cost and improves throughput for NAND and other non-volatile memory devices, which are increasing in capacity
The T5221 incorporates up to 12 test stations within a third-party multi-wafer prober, each with independent testing capabilities. This delivers the best floorspace efficiency for a non-volatile memory test system in Advantest’s history, without the need for additional footprint other than for the system controller. The tester’s massive parallelism allows it to perform wafer-level testing on up to 1,152 devices at once, improving throughput.
Advanced hardware and high-speed data transmission capability
As the capacity of 3D NAND devices increases, increased amounts of data output as test results have become harder to contend with. To offset the effects of these increases in data processing time, the T5221 delivers higher data transfer speeds. As a result, test times can be further shortened and throughput is improved over previous products.
Preserves compatibility with previous memory test systems
The T5221 uses Future Suite, an operating system for memory test systems that has a proven track record as the global standard. High compatibility with older systems provides users with a seamless transition from previous generations of equipment.
|Target Devices||NAND Flash, Other NVM|
|Overall Timing Accuracy||+/- 4,000ps|
|Software||FutureSuite OS (ATL and MPAT compatible)|