The new T5835 has full testing functionality, from package
testing to high-speed wafer testing, for any memory ICs with
operating speeds up to 5.4 Gbps, including all next-generation
memories from NAND flash devices to DDR-DRAM and LPDDR-DRAM. It
can handle 768 devices simultaneously for final package-level
testing. It additionally features functions such as an enhanced
programmable power supply (PPS) for advanced mobile memories,
and a real-time DQS vs. DQ function to improve yield.
The T5385’s timing training function, which is indispensable for
increasingly high-speed memory tests, and its high-speed
evaluation and defect analysis functions based on various device
data patterns, also help the new system address high device
capacities and speeds than previous products. These features
reduce test times and help improve yield. In addition, the new
system’s scalable structure enables future flexibility. An added
CPU for calculations increases its functionality, speed, and
capacity.
The T5835 inherits the proven T5800 series as the global
standard for memory test systems and further enhances the
platform scalability. Several models are available, including
the STH (Small Test Head), which is compact and suitable for
evaluation and analysis sites, the LTH (Large Test Head), which
is large and suitable for large-scale mass production for Final
Test, and MTH(Middle Test Head), which is capable of high-speed
wafer probing. The ability to select and offer the system
configuration best suited to the needs contributes to lower
initial investment and greater efficiency for customers. In
addition, the digital modules are upgradeable, providing a
continuous solution for future expansion needs.
